Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Verilog, C, Fpga, SW simulators, verification infrastructure, verification testbenches, systemverilog

Low Power Verification., C Programming, SoC Verification, systemverilog, Uvm, ARM SoC, Gate Level Simulation, Coverage Closure, APB, AHB, Axi

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Python, Perl, AHB, JasperGold, Uvm, formal verification, VC Formal, systemverilog, APB, Axi, AMBA protocols

Test Plans, CHI, tracing, test benches, Ace, breakpoints, ARM AMBA protocols, checkers, JTAG interface, ARM Core Sight, Agile software practices, Axi, hardware triggers, test generators, Coverage