rc extraction , routing, Static Timing Analysis, Perl, Tcl, Sta, CTS, synthesis DFT, LVS, sign-off, Netlist to GDS, Synthesis, GDS validation, deep sub-micron routing, scan validation, RTL to GDS, Floor Planning, Layout, Timing Closure, DRC, Placement, backend design EDA tools, clock tree insertion, Synopsys ICC2, EDA software