Tcl Scripting, Routing, Python, Layout violation resolution, floorplanning, Physical Verification, EM closure, Synopsys Fusion Compiler, Cadence Innovus, Physical design flows, Signal integrity analysis, Dfm, Timing Closure, Placement, Clock Tree Synthesis

Tcl, Verilog, Python, Perl, Computer Architecture, Cadence Innovus, EDA Tools, digital logic, Physical Design, Methodology