PYTHON, PERL, Verilog, Tcl, ATPG vector generation, DFT concepts, Digital circuit design, Logic BIST design and debug, Memory BIST insertion and verification, Scan compression, Static timing principles, IEEE 1149, Scan Insertion, VHDL, Testbench generation, device physics, Simulation and debug

Perl, Python, Tcl, Sta, Synthesis, DFT EDA tools, Dft

Perl, Python, Tcl, Sta, Synthesis, Dft, DFT EDA tools

boundary scan , IC logic design flows, STA timing analysis, IC verification flows, DFT design, ATE test patterns, pattern debugging, test issue analysis, MBIST, verification of automotive-grade SoCs, EDA tools from Synopsys, coverage optimization, ATPG, Scan, IC DFT

Verilog, SDF, Scripting Languages, Python, Linux, Perl, Tcl, Sta, Simulation, FPGA synthesis, test benches, RTL, DFT schemes, post-silicon debug, Synthesis, design flow, bench setup, MBIST, Gate, Transition and Path-Delay fault model, DFT tools, ATPG, Scan Compression, Scan, Stuck-at

Verilog, SDF, Python, Perl, Linux, Tcl, Sta, FPGA synthesis, RTL, Dft, Path-Delay fault model, post-silicon debug, Synthesis, design flow, bench setup, MBIST, Gate, Scan Compression at IP and SoC level, DFT tools, ATPG, Scan Compression, Scan, Stuck-at, Transition

SDF, Fpga, Perl, Tcl, Python, Dft, ATPG, Sta, RTL, Gate, MBIST