Unix, Linux, Perl, Scripting, Python, Tcl, digital IC design, EDA Tools, Mentor, Synopsys, Cadence Virtuoso

EDA Tools, SERDES, Mentor Graphics, Verification, Cadence, Analog Design, Synopsis

C, Makefile, Windows, Pcie, Verilog, System Verilog, Python, Linux, Perl, Ethernet, Systemc, IP level ASIC verification, acceleration HLS tools process, UPI verification, ChatGPT, SERDES, UVM based verification frameworks, TLM, MS-Copilot, UVM testbenches, automating workflows in a distributed compute environment, Co-Sim, Digital Design, simulation profile efficiency improvement, Analog Design, debugging firmware and RTL code using simulation tools

formal tools, EDA Tools, SERDES, Verification, Mentor Graphics, Cadence, Analog Design, Synopsis, functional verification tools