Transistor Level Design, Layout parasitics, FinFET, Circuit Design, Power noise variation, CMOS device physics, Standard cell libraries, IR analysis, Physical Design, Register files, GAA nanosheet architectures, Metal stacks, Characterization and verification of standard cells, RTL-to-GDS, Spice, SRAMs

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

Vcs, Verilog, Scripting Languages, Debug, verification methodologies, Simulation, Uvm, coverage infrastructure tools, VHDL, stimulus checking, NC, Verilator

Gerrit, Artifactory, Git, Jtag, Python, CloudBees, debug architecture, MBIST, CoreSight, Dft, trace scan, SoC debug ecosystems, ELA telemetry frameworks, on-chip debug architectures, IJTAG

Github, Jenkins, Pytest, Git, C, Verilog, System Verilog, Python, Git actions