CADENCE layout entry tools, ERC, CALIBRE DRC, LVS, Synopsys, Cadence Virtuoso

CADENCE layout entry tools, layout methodology, CALIBRE DRC ERC LVS, parasitic optimizing

Fin-FET, layout methodology, CADENCE layout entry tools, CALIBRE DRC ERC LVS, Synopsys

CADENCE layout entry tools, layout methodology, CALIBRE DRC ERC LVS, parasitic optimizing

C, Perl, Verilog, Python, Validation automation workflow optimization, Applied AI ML for test analytics and defect pattern analysis, Synopsys VCS, Test Algorithm Program Development, Silicon Debug Electrical Failure Analysis

Advanced process nodes, Mentor Calibre, DRC LVS tools, Synopsys Custom Compiler, High-speed SerDes PHY design, Post-layout optimization, Layout matching techniques, Custom IC layout design, Cadence Virtuoso Layout XL GXL

MATLAB, Python, SOI technologies, FinFET, Cadence, analog fundamentals, noise analysis, Ads, HBM, SERDES, EDA Tools, Stability, 6.4 Gbps, Verilog-A, LPDDR5, AMs, feedback systems, Spectre, EMX, Hspice, virtuoso, scripting skills, DDR protocols, DDR5, JEDEC, DDR4