CADENCE layout entry tools, CALIBRE DRC ERC LVS, Synopsys, Cadence Virtuoso

Fin-FET, layout methodology, CADENCE layout entry tools, CALIBRE DRC ERC LVS, Synopsys

PERL, Tcl, Cadence Tools, Skill, CALIBRE DRC

C, Perl, Verilog, Python, Validation automation workflow optimization, Applied AI ML for test analytics and defect pattern analysis, Synopsys VCS, Test Algorithm Program Development, Silicon Debug Electrical Failure Analysis

Advanced process nodes, Mentor Calibre, DRC LVS tools, Synopsys Custom Compiler, High-speed SerDes PHY design, Post-layout optimization, Layout matching techniques, Custom IC layout design, Cadence Virtuoso Layout XL GXL