constraint analysis , Perl, Verilog, System Verilog, Tcl, Sta, Synthesis, Simulation, synthesis logic equivalence, timing constraints generation, STA tools and flow, design for test, IP ASIC timing constraints generation, Dft, formal verification, backend related methodology and tools, LINT, Timing Closure, Design Methodologies, functional coverage, timing closure of various test modes

synopsys primetime , Perl, Python, Tweaker, Power-Aware Verification UPF, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, Cadence Conformal LEC, PrimeClosure, Cadence Tempus, Synopsys Formality, Formal Verification LEC, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass, Timing Closure ECO Cadence Tempus

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design

Shell, Perl, Analog Design Environment, Analog Design Flow, Virtuoso Schematic Editor, Virtuoso Layout Features

Test automation, Integration And System Testing, Qualification of Vendors, Six Sigma Methodology, Exposure to Regulatory Standards Manufacturing process and procedure for, Systems Component level Verification Validation, Understanding of hardware methodologies and test best practices, IQ OQ and PQ for equipments Instruments, Design verification and validation of medical devices, Technical testing reliability experience in Plastic Connectors Products electro-mechanical, RF welding Solvent bonding process, Statistical tools like Minitab

Phase Interpolator, SERDES, Driver, Circuit Simulation, Physical Verification, Deserializer, Layout, CMOS design, Bias and Bandgap Voltage Regulators, Receiver, jitter and signal equalization techniques, High Speed Clock Distribution, Serializer, Low jitter PLL