CADENCE layout entry tools, CALIBRE DRC ERC LVS, Synopsys, Cadence Virtuoso

CADENCE layout entry tools, ERC, CALIBRE DRC, LVS, Synopsys, Cadence Virtuoso

CADENCE layout entry tools, layout methodology, CALIBRE DRC ERC LVS, parasitic optimizing

C, Perl, Verilog, Python, Validation automation workflow optimization, Applied AI ML for test analytics and defect pattern analysis, Synopsys VCS, Test Algorithm Program Development, Silicon Debug Electrical Failure Analysis

Advanced process nodes, Mentor Calibre, DRC LVS tools, Synopsys Custom Compiler, High-speed SerDes PHY design, Post-layout optimization, Layout matching techniques, Custom IC layout design, Cadence Virtuoso Layout XL GXL

ASIC design flow, Standard bus protocols, DFT concepts, Verilog Hdl, Synthesis timing analysis, Cadence, Peripheral interface design, AMBA, Axi, APB, EDA Tools, DMA, Bus systems, Compiler principles, Low-power design methodologies, Synopsys, AHB, Cache architectures