SDF, Fpga, Perl, Tcl, Python, Dft, ATPG, Sta, RTL, Gate, MBIST

Verilog, SDF, Scripting Languages, Python, Linux, Perl, Tcl, Sta, Simulation, FPGA synthesis, test benches, RTL, DFT schemes, post-silicon debug, Synthesis, design flow, bench setup, MBIST, Gate, Transition and Path-Delay fault model, DFT tools, ATPG, Scan Compression, Scan, Stuck-at