CADENCE layout entry tools, layout methodology, CALIBRE DRC ERC LVS, parasitic optimizing

Power Bi, Vba, Tableau, Python, Sql, Statistical Analysis, advanced packaging, JEDEC standards, data visualization tools, HBM technology, Jmp

parasitic optimizing, CADENCE layout entry tools, layout methodology, CALIBRE DRC ERC LVS

Scripting, Statistics, Verilog simulations, Data analysis tools, Product Engineering, Electrical and Electronics Engineering, CAD Tools

distributed architecture , Api Development, Java, multi-threading, Microservices, Distributed Computing, Springboot, Kafka, Machine Learning, Python, Databases, AI infrastructure, vector DB, SpringCloud, Langchain, messaging frameworks, generative AI

Tcl Scripting, Routing, Python, Layout violation resolution, floorplanning, Physical Verification, EM closure, Synopsys Fusion Compiler, Cadence Innovus, Physical design flows, Signal integrity analysis, Dfm, Timing Closure, Placement, Clock Tree Synthesis

UNIX, Linux, Bash, Tcl, Physical Verification, Detailed routing, Cadence, Placement, EDA Tools, Siemens, Clock Tree Synthesis, Synopsys, formal verification, Timing Analysis