P R formal verification, automatic physical design platform, power analysis, Design for reliability, physical design methodology, tape-out, Physical Verification, Place Route

power integrity , Physical Design, electromagnetic compatibility, Cadence Innovus, Logic Synthesis, Physical Implementation, Synopsys ICC2

Partitioning, floorplanning, Cadence Innovus, Cross-block timing closure, Synopsys ICC2

Synopsys IC Validator, PERC, Mentor Calibre, Reliability checks, Esd, ERC, DRC, LVS, GDS scramble, ANT fill program