Job Description

THE ROLE:

As a New Product Introduction Engineer, you will drive product cost through Yield improvement, quality with test content and test points design, and product definition/bounding box development. You will work closely with world class Product Test, Design, Quality, Reliability, Customer, Software and Platform global teams to plan and develop the final product solution to meet KPI targets. With close collaboration with end customer, you will also have insights into the product and guide your team to achieve customer expectations

We are the high-end test engineering team providing test solutions for Data Center Graphics (DCG) New Product Introduction (NPI) under the Product Engineering Organization. We do exciting product development for leading-edge technology that will power the next generation processors used for high performance computing, data centers, enterprise servers, and Artificial Intelligence clusters.

If you are looking for a fulfilling and challenging career as an engineer leading NPI ATE Product Development, you are at the right place! As a (Senior) MTS Product Development Engineer, you will be responsible for developing and driving ATE test solution to meet NPI business milestones and KPI (test time, yield, cost, quality). The expectation is to perform leadership through interaction with design teams, Product & Test Engineering teams, Quality & Reliability teams, software & platform teams to come up with the best solution that balance quality and cost. You will experience working with and learning from AMD's talented engineering teams around the world.

THE PERSON:

We are looking for someone with strong technical, analytical, leadership and problem-solving skills, as well as demonstrating the characteristic of an independent and resourceful individual. Preferably, the candidate should have high understanding of product development ecosystem. The candidate should possess good communication skills as this is the key to successful collaboration.

The applicant must have a strong background in Integrated Voltage Regulator (IVR) testing and characterization, with hands-on expertise in Teradyne or Advantest ATE platforms. In this role, you will be responsible for developing and executing test solutions for IVRs used in advanced SoC and power management applications. You will work closely with design, product, and validation teams to ensure robust test coverage, yield optimization, and reliable product performance.

KEY RESPONSIBILITIES:

Lead engineering efforts in silicon characterization and analysis to define products that meet customer requirements, yield, and cost targets.
Provide technical leadership across PEO teams, aligning design feedback, customer requirements, and product goals.
Represent PEO in design discussions, influencing decisions that significantly impact final product outcomes.
Conduct gate reviews for test, cost, and quality at key development milestones.
Drive timely resolution of customer-reported issues in collaboration with quality and support teams.
Develop ATE test programs and hardware (e.g., load boards, probe cards) for validation, characterization, and production testing of IVRs.
Utilize platforms such as Teradyne (UltraFlex, J750) and Advantest (V93000, T2000) to implement and debug analog/mixed-signal test routines.
Support test development from pre-silicon through high-volume manufacturing, including PVT characterization and detailed reporting.
Perform power-related testing (e.g., PSRR, efficiency, transient response) and stability analysis.
Collaborate with design and systems teams to define test specifications and translate design intent into executable test plans.
Automate data collection and analysis using tools like Python, MATLAB, or JMP.
Lead root-cause analysis of silicon issues using both ATE and bench-level tools.
Drive initiatives for test time reduction, yield enhancement, and cost optimization.

PREFERRED EXPERIENCE:

Over 7 years of experience in the semiconductor industry, with a strong foundation in analog/mixed-signal IC testing and ATE development.
Skilled in data extraction, manipulation, and visualization using statistical tools such as correlation analysis, predictive modeling, contrast analysis, and machine learning.
Proficient in wafer, final test (FT), and system-level test (SLT) methodologies and equipment.
Solid understanding of Design of Experiments (DOE), failure analysis, and RMA processes.
Background in solid-state physics, computer architecture, and both digital and analog design.
Experienced in Python for data analysis, SQL for database queries, and scripting in C, C++, Java, Ruby, and Perl.
Strong command of Excel, JMP, Yield Explorer, SAS, Power BI, and other EDA tools.
Comfortable working across Windows and Unix/Linux environments.
Proven ability to manage multiple projects under tight deadlines with strong communication and organizational skills.
Hands-on experience with on-die and integrated voltage regulators in advanced CMOS nodes.
Familiar with high-volume manufacturing, test correlation between ATE and bench, and reliability qualification (ESD/Latch-up, HTOL).
Knowledgeable in test hardware design and debugging (probe cards, load boards), and test cost optimization techniques.
Proficient in developing/debugging test programs on Teradyne and Advantest ATE platforms.
Strong grasp of power management circuits including buck/boost converters, LDOs, and SVI3/I2C/I3C protocols.
Experienced with lab instrumentation such as oscilloscopes, SMUs, electronic loads, and network analyzers.
Skilled in silicon bring-up, PVT characterization, and yield analysis with robust troubleshooting capabilities

ACADEMIC CREDENTIALS:

BS/MS Electrical Engineering, Computer Engineering, or comparable disciplines

LOCATION:

Singapore

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