CI CD via tools such as Confluence Git JIRA, processor architecture knowledge ARM RISC-V ISA symmetric multiprocessing cache architecture SIMD Vector Processing custom instructions, Python for prototyping demo verification and or automation, OS GNU Linux proprietary RTOS Bare metal, ANSI C bare-metal design implementation optimization and debugging using GCC-like toolchains, software hardware and FPGA debugging capability

JIRA, Rtos, Arm, Python, Confluence, Git, Isa, Vector Processing, Bare metal, ansi c, GCC-like toolchains, simd, processor architecture knowledge, CI CD, RISC-V, GNU Linux, FPGA debugging, symmetric multiprocessing, custom instructions, cache architecture