bump , C, Python, Perl, Pi, Fc, Tcl, INVS, Pr, Pt, Pv, PX, signoff standards, digital physical design flow, power analysis flows, Calibre, EDA Tools, STA analysis methods, 3D IC design, FC synthesis, low-power design methodologies, ESD planning, RTL to GDS, RH, PPA optimization

Sta, Spice signoff, PPAC optimization, placement routing, semiconductor design methodologies, Physical Verification, IR analysis, power and performance verification, EDA Tools, Timing Closure, back-end implementation flow, advanced process nodes, GDSII

Sta, Spice signoff, IR signoff, PPAC optimization, back-end physical implementation, GDSII layout design, Layout Design

rc extraction , routing, Static Timing Analysis, Perl, Tcl, Sta, CTS, synthesis DFT, LVS, sign-off, Netlist to GDS, Synthesis, GDS validation, scan validation, Layout, RTL to GDS, Floor Planning, DRC, Timing Closure, Placement, backend design EDA tools, clock tree insertion, Synopsys ICC2, EDA software

rc extraction , routing, Static Timing Analysis, Perl, Tcl, Sta, CTS, synthesis DFT, LVS, sign-off, Netlist to GDS, Synthesis, GDS validation, scan validation, Layout, Floor Planning, RTL to GDS, Timing Closure, DRC, Placement, backend design EDA tools, clock tree insertion, Synopsys ICC2, EDA software