Tcl Scripting, Routing, Python, floorplanning, Layout violation resolution, Physical Verification, EM closure, Cadence Innovus, Synopsys Fusion Compiler, Physical design flows, Signal integrity analysis, Dfm, Timing Closure, Placement, Clock Tree Synthesis

Tcl Scripting, Routing, Python, Layout violation resolution, floorplanning, Physical Verification, EM closure, Synopsys Fusion Compiler, Cadence Innovus, Physical design flows, Signal integrity analysis, Dfm, Timing Closure, Placement, Clock Tree Synthesis

Nvme, Pcie, Continuous Integration, test automation, Python Programming, Agile Development, GIT development flow, SSD firmware testing, automated build

Java, Golang, Cassandra, Bash, HBase, Redis, Terraform, Kubernetes, Python, Airflow, Step Functions, GitOps, Cadence, Temporal, ArgoCD

USB type C Power Delivery, Test scripts development in Python or other Programming languages, FPGA development with RTL design, Digital and analog circuit design, USB3.2 SuperSpeed, Microprocessor system architecture and development

Matlab, Python, FD-SOI technologies, industrial testing, Cadence-Virtuoso, Digital Design, CMOS, millimetre-Wave architecture, Bi-CMOS, DFT test development, RF architecture, Analog Design

transceivers , regulators , High Speed Serdes, design rules for advanced process nodes, Filters, semiconductor device physics, ESD Latchup standards, Analog Circuit Design, Spectre, protection techniques, input matching network, Amplifiers, EDA Tools, Spice, Cadence Virtuoso, analog blocks

parasitic optimizing, CADENCE layout entry tools, layout methodology, CALIBRE DRC ERC LVS

Test Methodology, UltraFlex test handler, yield analysis, Adventest 93K, quality management tools, debugging skills, wafer prober